Computer systems employing the SL enhanced 80486 microprocessor manufactured by Intel and successor microprocessors in the x86 family enable a system management mode (SMM) of operation. The SMM can be used by system firmware to control product specific hardware features in a manner that is transparent to the computer operating system and applications programs. The SMM management mode is typically used for system management information such as the system configuration, or the configuration of a powered down microprocessor or to invoke power saving features such as a zero volt suspend function.
The SMM is subject to inefficiencies in computers employing DOS or Windows operation systems. When operating in SMM the microprocessor accesses a dedicated and separate memory called the system management random access memory (SMRAM). The SMRAM can be implemented in two ways. First, the SMRAM can occupy an area of memory having a unique addressable locations. This is known as non-overlayed memory. If this implementation of SMRAM is employed, then the microprocessor may employ internal cache memory to store data and instructions from the SMRAM. In DOS compatible systems the first 1 megabyte of memory, corresponding to the 20 bit address of the Intel 8086, is mapped according to software compatibility requirements which are a legacy of the selections made in the original IBM personal computer. Thus non-overlayed SMRAM must be located beyond the first 1 megabyte of memory. This results in computer architecture restrictions associated with this memory space higher than 1 megabyte. For example, far jumps are restricted and the program code size is limited to 64 kilobyte segments. Due to these restrictions, non-overlayed SMRAM is not often employed.
The second SMRAM implementation is more commonly used in personal computers. The SMRAM is addressed in a second, separate address space which overlaps an area of system memory within the first one megabyte of memory. Note that the legacy software restrictions require that the SMRAM overlay some portion of normal memory which is generally used for another purpose when not in SMM. When the processor is in normal mode, the external memory system accesses the system memory normally. When the processor is in SMM, the external memory system remaps the memory accesses to a separate system management memory having addresses within the system memory. The microprocessor is unaware of this external memory remapping.
This causes a problem in using the internal cache memory of the microprocessor. Because the microprocessor takes no part in the memory remapping, it cannot differentiate between normal system memory and SMRAM. Thus cache coherency cannot be maintained when using both the normal mode and the SMM. This may be avoided by treating the SMRAM as non-cachable. Of course this negates the value of the microprocessor internal cache. Current microprocessors often operate at higher instruction rates than the system bus rate. Thus the microprocessor operates much slower if the cache cannot be used. This cache coherency problem may also be avoided by cache flushing upon entry into and exit from SMM. A cache flush invalidates entries not changed since being recalled from external memory and writes back to memory dirty entries, i.e. cache entries that have been changed since being recalled from external memory. With the trend toward larger and larger internal caches, such a cache flush may take a long time. Further, a larger cache is less likely to require all prior cache entries be cleared in order to service the SMM program instruction fetches and data loads, thus many cache entries may be flushed unnecessarily. Both the alternatives make ineffective use of the internal cache of the microprocessor. At the same time, there is a trend toward greater and greater use of SMM applications. This means that the ineffective use of internal cache is becoming more critical.
A solution enabling caching of system management memory is described in U.S. Pat. No. 5,544,344 APPARATUS FOR CACHING SMRAM IN AN INTEL PROCESSOR BASED COMPUTER SYSTEM EMPLOYING SYSTEM MANAGEMENT MODE. This patent proposes using a SMIACT bit, which indicates whether the microprocessor is in normal mode or in system management mode, in a manner as a most significant address bit. Thus if the SMIACT bit is "0" indicating normal mode, data and instructions are cached normally. If the SMIACT bit is "1" indicating system management mode, this bit selects another memory space. This patent also teaches checking the address against an address range assigned to the SMRAM on every cache access. Thus data and instructions within the system management memory may be cached along side data and instructions from normal memory.
This solution has a disadvantage. This solution requires that the number of bits in the cache tag table be extended one additional bit to cover the SMIACT bit effectively used as the most significant bit of the address. Thus each cache line requires an additional tag bit. With the trend toward larger and larger internal caches, the extra area required for these additional cache tag bits becomes significant.